An increasingly significant consideration in chip design is power consumption. This includes not just the overall power consumption, but the distribution of localized power consumption and not just the time-averaged but the maximum instantaneous power consumption.
The placement of logical units within the floorplan of a chip significantly determines power consumption. The terms “logical unit,” “logic,” and “unit” as used herein each have their industry standard meaning and may further refer to one or more: circuits, components, registers, processors, software, or any combination thereof. In particular, power consumption is determined by the amount of activity within logical units. The amount of activity in logical units can be estimated by simulations.
What is needed is a system and method with an effective way to associate simulation information to distributed, localized power consumption within the floorplan of a chip, visualize the power consumption, and use the associated information to improve the distribution.